instruction cache造句
例句与造句
- If there is no instruction cache , this subroutine may be a no - op
如果在你的目标机上，没有指令缓存，则可能不做任何操作。 - Instruction to invalidate the instruction cache line that will contain the modified instruction
指令，使将要存放修改后指令的指令高速缓存行无效。 - On sparc and sparclite only , write this subroutine to flush the instruction cache , if any , on your target machine
只在sparc和sparclite平台上，这一功能调用用来刷新指令缓存。 - It is a risc microprocessor , has a six - stage pipeline , with separated data cache and instruction cache
银河ts - 1采用典型的risc结构，六级流水线，具有独立的指令cache和数据cache 。 - In order to gain more performance improvement 8k data cache and 8k instruction cache are used in ck510
这些改进使c - core性能大大超过m - core 。整数运算能力是嵌入式cpu中重要的性能指标。 - It's difficult to find instruction cache in a sentence. 用instruction cache造句挺难的
- The fetcher generates a fetch address for fetching a cache block from the instruction cache containing instructions to be executed
指令读取器产生读取位址以供快取记忆体读取快取区块内的指令。 - On target machines that have instruction caches , gdb requires this function to make certain that the state of your program is stable
在有指令缓存的目标机上， gdb需要这一函数，以确定你的程序的状态是稳定的。 - An instruction cache miss will occur when fetching this instruction , resulting in the fetching of the modified instruction from storage
当取这个指令时会发生指令高速缓存失败，结果就会从存储器中取得修改后的指令。 - And in fact , the problem is exacerbated by the fact that a media app pushes data through the data cache much faster than a static app pushes code through the instruction cache
事实上，这是由于动态媒体程序需要以远远高于静态程序填充指令的速度来填充数据。 - This paper presents the logic circuit design of ccu for lx - 1164 cpu chip , for ccu , data and instructions are stored in separate data and instruction caches
本人有幸在夏宏博士的指导下参加这一工程，承担lx ? 1164cpu的高速缓存控制器( ccu )的逻辑设计和功能仿真。 - This paper discusses msu ' s design , implementation and verification , implements the integration of the " longtengrl " system and studies the optimization of instruction cache
本课题组设计的“龙腾r1 ”微处理器芯片，指令系统与motorola公司的powerpc603e兼容，体系结构自主设计。 - The performance is improved significantly . the average ipc speedup is 6 . 9 % . 3 . prefetching policy using miss queue information is proposed by investigating instruction cache misses and data cache misses
3 .通过对指令cache和数据cache失效行为的分析,提出一种预取策略? ?结合访存失效队列状态的预取策略。 - Several methods to reduce the circuit switch activity are developed . pre - visiting tag technique is used to reduce the instruction cache activity . base address locality technique is used to reduce the data cache activity
并从减少电路活动性角度出发，开发出减少指令cache功耗的预访问技术，以及减少数据cache功耗的基地址相关技术。 - This thesis addresses itself to the designing and implementation of the multi - level memory system of dpc , including the register files , instruction cache , data cache and the on - chip memory , which is called scratch - pad sram
本文采用了多层次的存储体系结构,包括分体寄存器文件、分离的指令、数据cache以及片上存储器scratch - padsram 。 - It has five parts , such as integer execution unit , floating point unit ( fpu ) , instruction cache , bus interface unit and memory manage unit . the instructions are executed with pipeline way . the instruction set and i / o signals are compatible with powerpc
它由定点执行单元、浮点单元、指令cache 、总线接口单元、存储管理单元组成，以流水和超标量方式执行指令，指令集和接口时序兼容powerpc ，是典型的risc微处理器结构。
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